The ability to drive large load capacitance while maintaining minimum propagation delay and keeping circuit complexity low is difficult to achieve in sub-micron logic gates operating in the 3.0-3.6 v power supply range.
A CMOS solution to the problem involves increasing output transistor gate widths to obtain good drive capability. But this approach has problems with excessive silicon area use and increased input capacitance which slows the input signal. Use of multiple stages with a 1:3 drive strength ratio reduces input loading but at the expense of silicon area and complexity. A limit to the minimum propagation delay is also set by the number of stages used.
A bipolar approach to solving the problem offers the best drive capability in terms of silicon area required. There are presently three bipolar solutions:
1) BiNMOS. The BiNMOS (2 input NAND gate) circuit 10 of FIG. 1 uses a bipolar transistor 12 to provide good pull up drive capability. Pull down drive, however, is implemented with N-channel CMOS transistors 14, 16, 18 and 20, which has the problems already pointed out for CMOS. BiNMOS also performs a portion of the logic function in the pull down section which leads to stacking of N-channel transistors. This also further reduces pull down drive capability. PA1 2) BiCMOS. The BiCMOS (2 input NAND gate) circuit 22 of FIG. 2 offers good pull up and pull down drive capability with Vcc in the 4.5-5.5 v range. Performance rapidly degrades as Vcc is reduced below 4 volts. At lower supply voltages the gate to source voltage of transistors 24 and 26 is greatly reduced due to the base-emitter voltage of transistor 30. The reduction in drain current results in less drive for transistor 30 which degrades pull down drive. PA1 3) QCBiCMOS. The Quasi-Complementary BiCMOS (2 input NAND gate (QCBiCMOS)) circuit 32 of FIG. 3 has been shown to provide good performance for sub-micron logic gates operating in the 3.0-3.6 volt power supply range. See Ref 1. Yano et al., "Quasi-Complementary BiCMOS for Sub-3-V Digital Circuits," IEEE Journal of Solid State Circuits, vol. 26, no. 11, pp 1708-1719, Nov. 1991. Equations are derived in reference 1 that show QCBiCMOS delay is proportional to (CLOAD)**(1/3), BiCMOS delay proportional to (CLOAD)**(1/2), and CMOS delay proportional to (CLOAD)**(1.00). QCBiCMOS clearly has the best performance. QCBiCMOS delay dependence on the power supply voltage is also shown to not be a problem until Vcc approaches 2.0 v.
A problem with QCBiCMOS, as presented in ref. 1 of Yano et al., is circuit complexity. As seen in FIG. 3, individual gates G1 and G2 are used to drive pull up nodes N1 and pull down node N2. Sizing used in gates G1 and G2 provide some performance advantage but at the expense of increased macro complexity. As the macro's logic function complexity increases it becomes clear using individual gates to provide separate drive to pull up and pull down nodes has a silicon area penalty. Another problem with QCBiCMOS is the manner in which the pull down transistor, 36, is turned off. In FIG. 3, feedback inverter G3 signals transistor 38 to turn on and discharge transistor 36 saturation charges when the output reaches a logic low. The problem involves the timing of the feedback signal. If the signal arrives too soon, base drive needed for transistor 36 can be diverted away through transistor 38. The feedback inverter is sized to prevent this from occurring. If the signal is delayed too much, however, and does not arrive before the next pull up transition, a transistor 34-36 short circuit condition can occur. Transistor 36 will still be in an on state while transistor 34 is supplying pull up drive. Providing a properly timed clamp signal that satisfies all possible output loading conditions with the method shown in FIG. 3 is found to be a problem.